refactor(joinir): Phase 260 P0.1 Step 1 - Create rewriter/ skeleton (box-first modularization)

Create rewriter/ directory with re-export skeleton for instruction_rewriter.rs.
This enables gradual refactoring without breaking existing code.

Changes:
- NEW: src/.../joinir/merge/rewriter/mod.rs (re-exports instruction_rewriter)
- CHANGED: merge/mod.rs - route calls through rewriter module
- STRATEGY: Keep instruction_rewriter.rs intact, split later into:
  - terminator.rs (Branch/Jump/Return remapping)
  - exit_line.rs (ExitLine/exit-phi wiring)
  - carriers.rs (loop_invariants, exit_bindings)
  - logging.rs (DEBUG-177 style verbose logs)

Acceptance:
- cargo check PASS ✅
- No behavior change (挙動変更なし)
- Backward compatible (instruction_rewriter.rs still exists)

Next: Extract terminator.rs (smallest, safest first split)

src/mir/builder/control_flow/joinir/merge/mod.rs

@@ -19,7 +19,8 @@ pub mod exit_args_collector; // Phase 118: Exit args collection box
 pub mod exit_line;
 mod exit_phi_builder;
 mod expr_result_resolver;
-mod instruction_rewriter;
+mod instruction_rewriter; // Phase 260 P0.1: Keep for gradual migration
+mod rewriter; // Phase 260 P0.1: New modularized rewriter (forwards to instruction_rewriter)
 mod loop_header_phi_builder;
 mod loop_header_phi_info;
 mod merge_result;
@@ -885,7 +886,8 @@ pub(in crate::mir::builder) fn merge_joinir_mir_blocks(
     // Phase 4: Merge blocks and rewrite instructions
     // Phase 33-16: Pass mutable loop_header_phi_info for latch_incoming tracking
     // Phase 177-3: Pass exit_block_id from allocator to avoid conflicts
-    let merge_result = instruction_rewriter::merge_and_rewrite(
+    // Phase 260 P0.1: Use rewriter module (re-exports instruction_rewriter)
+    let merge_result = rewriter::merge_and_rewrite(
         builder,
         mir_module,
         &mut remapper,
@@ -899,7 +901,7 @@ pub(in crate::mir::builder) fn merge_joinir_mir_blocks(
 
     // Phase 4.5: Finalize loop header PHIs (insert into header block)
     //
-    // By now, instruction_rewriter has set latch_incoming for all carriers.
+    // By now, rewriter has set latch_incoming for all carriers.
     // We can finalize the PHIs and insert them into the header block.
     if !loop_header_phi_info.carrier_phis.is_empty() {
         trace.stderr_if(

src/mir/builder/control_flow/joinir/merge/rewriter/mod.rs

@@ -0,0 +1,31 @@
+//! Instruction Rewriter - Modularized
+//!
+//! Phase 260 P0.1: Boxed modularization of instruction_rewriter.rs
+//! Split large file (1477 lines) into focused, single-responsibility modules.
+//!
+//! ## Module Structure
+//!
+//! - `terminator`: Terminator remapping (Branch/Jump/Return conversion)
+//! - `exit_line`: Exit value collection (ExitLine/exit-phi wiring)
+//! - `carriers`: Carrier management (loop_invariants, exit_bindings)
+//! - `logging`: Debug logging (DEBUG-177 style, verbose flag control)
+//!
+//! ## Public API (re-exported)
+//!
+//! - `is_skippable_continuation`: Structural check for skippable continuation functions
+//! - `merge_and_rewrite`: Main orchestrator for JoinIR→MIR merge
+
+// Phase 260 P0.1 Step 1: Forward all declarations to parent instruction_rewriter.rs
+// This allows gradual migration without breaking existing code.
+//
+// When modules are ready:
+// - mod terminator;
+// - mod exit_line;
+// - mod carriers;
+// - mod logging;
+//
+// For now, re-export from parent to maintain compatibility.
+
+// Re-export public API from parent instruction_rewriter module
+pub(super) use super::instruction_rewriter::is_skippable_continuation;
+pub(super) use super::instruction_rewriter::merge_and_rewrite;