89a9212700
Key changes: - Phase 83-1: Switch dispatch fixed mode (tiny_inline_slots_switch_dispatch_fixed_box) - NO-GO (marginal +0.32%, branch reduction negligible) Reason: lazy-init pattern already optimal, Phase 78-1 pattern shows diminishing returns - Allocator comparison baseline update (10-run SSOT, WS=400, ITERS=20M): tcmalloc: 115.26M (92.33% of mimalloc) jemalloc: 97.39M (77.96% of mimalloc) system: 85.20M (68.24% of mimalloc) mimalloc: 124.82M (baseline) - hakmem PROFILE correction: scripts/run_mixed_10_cleanenv.sh + run_allocator_quick_matrix.sh PROFILE explicitly set to MIXED_TINYV3_C7_SAFE for hakmem measurements Result: baseline stabilized to 55.53M (44.46% of mimalloc) Previous unstable measurement (35.57M) was due to profile leak - Documentation: * PERFORMANCE_TARGETS_SCORECARD.md: Reference allocators + M1/M2 milestone status * PHASE83_1_SWITCH_DISPATCH_FIXED_RESULTS.md: Phase 83-1 analysis (NO-GO) * ALLOCATOR_COMPARISON_QUICK_RUNBOOK.md: Quick comparison procedure * ALLOCATOR_COMPARISON_SSOT.md: Detailed SSOT methodology - M2 milestone status: 44.46% (target 55%, gap -10.54pp) - structural improvements needed 🤖 Generated with Claude Code Co-Authored-By: Claude Sonnet 4.5 <noreply@anthropic.com>
184 lines
5.9 KiB
Markdown
184 lines
5.9 KiB
Markdown
# Phase 76-0: C7 Per-Class Statistics Analysis (SSOT化)
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## Executive Summary
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**Definitive C7 Statistics from Mixed SSOT Workload:**
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- **C7 Hit Count: 0** (ZERO allocations)
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- **C7 Percentage: 0.00%** of C4-C7 operations
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- **Verdict: NO-GO for C7 P2 (inline slots optimization)**
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---
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## Test Configuration
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**Binary**: `bench_random_mixed_hakmem_observe` (with HAKMEM_MEASURE_UNIFIED_CACHE=1)
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**Environment Variables**:
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```bash
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HAKMEM_WARM_POOL_SIZE=16
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HAKMEM_TINY_C5_INLINE_SLOTS=1
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HAKMEM_TINY_C6_INLINE_SLOTS=1
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```
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**Benchmark Parameters**:
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- Iterations: 20,000,000
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- Working Set Size: 400
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- Runs: 1 (per-class stats are cumulative)
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**Unified Cache Initialization**:
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```
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C4 capacity = 64 (power of 2)
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C5 capacity = 128 (power of 2)
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C6 capacity = 128 (power of 2)
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C7 capacity = 128 (power of 2)
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```
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---
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## Results: Per-Class Statistics
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### C7 Statistics (CRITICAL FINDING)
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| Metric | Value |
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|--------|-------|
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| Hit Count | 0 |
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| Miss Count | 0 |
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| Push Count | 0 |
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| Full Count | 0 |
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| **Total Allocations** | **0** |
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| **Occupied Slots** | **0/128** |
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| Hit Rate | N/A |
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| Full Rate | N/A |
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**Status**: C7 received **ZERO allocations** in the Mixed SSOT workload.
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### C4-C7 Ranking (Cumulative)
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| Class | Hit Count | Miss Count | Capacity | Hit % | Percentage of Total |
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|-------|-----------|-----------|----------|-------|---------------------|
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| C6 | 2,750,854 | 1 | 128 | 100.0% | **57.17%** |
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| C5 | 1,373,604 | 1 | 128 | 100.0% | **28.55%** |
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| C4 | 687,563 | 1 | 64 | 100.0% | **14.29%** |
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| C7 | 0 | 0 | 128 | N/A | **0.00%** |
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| **TOTAL** | **4,812,021** | **3** | — | — | **100.00%** |
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### Coverage Analysis
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| Cumulative Classes | Operations | Percentage |
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|--------------------|------------|-----------|
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| C6 alone | 2,750,854 | 57.17% |
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| C5+C6 | 4,124,458 | 85.72% |
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| **C4+C5+C6** | **4,812,021** | **100.00%** |
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| C4+C5+C6+C7 | 4,812,021 | 100.00% (no change) |
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---
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## Decision Analysis
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### Threshold Criteria
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- **GO for C7 P2**: C7 > 20% of C4-C7 operations
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- **NEUTRAL**: 15% < C7 ≤ 20% of C4-C7 operations
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- **CONSIDER C4 redesign**: C7 ≤ 15% of C4-C7 operations
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### Verdict: **NO-GO for C7 P2**
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**C7: 0.00%** - Falls far below any viable threshold
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**Explanation:**
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1. **Zero Volume**: The Mixed SSOT workload (128-1024B allocations) does NOT generate any C7 (1024-2048B) allocations.
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2. **Workload Mismatch**: The benchmark parameters (400 working set size, 20M iterations) are tuned to exercise C4-C6 intensively but avoid C7 entirely.
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3. **No Optimization Benefit**: Any C7 P2 (inline slots) optimization would provide 0% improvement for this specific workload.
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4. **Resource Opportunity Cost**: Engineering effort for C7 P2 would be better spent on C4 (14.29%) or investigating alternative workloads.
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---
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## Recommended Next Phase
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### Phase 76-1: C4 Per-Class Deep Dive
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**Objective**: Analyze C4 (14.3% of total operations) as the next optimization target
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**Rationale**:
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- C4 is the **largest remaining bottleneck** after C5+C6 inline slots
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- C4 (256-512B) represents a significant portion of tiny allocations
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- After C5/C6 optimizations (85.7%), C4 becomes critical for overall performance
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**Investigation Areas**:
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1. **C4 Hit Rate**: Currently 100.0% (full cache hits) - room for miss reduction?
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2. **C4 Cache Occupancy**: 63/64 slots occupied (near full)
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3. **C4 Allocation Pattern**: Is there temporal locality opportunity?
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4. **Alternative**: Investigate workloads that DO use C7 (system-level, long-lived objects)
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**Suggested Implementation Options**:
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- C4 LIFO optimization (vs current FIFO-like behavior)
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- C4 spatial locality improvements
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- C4 refill batching (similar to C5/C6)
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- Hybrid C4-C5 inline slots strategy
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---
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## Artifacts
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### Raw Log
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Location: `/tmp/phase76_0_c7_stats.log`
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Key excerpts:
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```
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[Unified-STATS] Unified Cache Metrics:
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[Unified-STATS] Consistency Check:
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[Unified-STATS] total_allocs (hit+miss) = 5327287
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[Unified-STATS] total_frees (push+full) = 1202827
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C2: 128/2048 slots occupied, hit=172530 miss=1 (100.0% hit), push=172531 full=0 (0.0% full)
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C3: 128/2048 slots occupied, hit=342731 miss=1 (100.0% hit), push=342732 full=0 (0.0% full)
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C4: 63/64 slots occupied, hit=687563 miss=1 (100.0% hit), push=687564 full=0 (0.0% full)
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C5: 75/128 slots occupied, hit=1373604 miss=1 (100.0% hit), push=0 full=0 (0.0% full)
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C6: 42/128 slots occupied, hit=2750854 miss=1 (100.0% hit), push=0 full=0 (0.0% full)
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[C7 MISSING - 0 operations]
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Throughput = 46152700 ops/s [iter=20000000 ws=400] time=0.433s
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```
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### Verification Output
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```
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C7 Initialization: ✓ Capacity=128 allocated
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C7 Route Assignment: ✓ LEGACY route configured
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C7 Operations: ✗ ZERO allocations
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C7 Carve Attempts: 0 (no operations triggered)
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C7 Warm Pool: 0 pops, 0 pushes
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C7 Meta Used Counter: 0 total operations
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```
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---
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## Key Insights
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1. **Workload Characterization**: The Mixed SSOT benchmark is optimized for C4-C6 (128-1024B). This is intentional and appropriate for most mixed workloads.
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2. **C7 Market Opportunity**: C7 (1024-2048B) allocations appear in:
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- Long-lived data structures (hash tables, trees)
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- System-level workloads (networking buffers)
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- Specialized benchmarks (not representative of general use)
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3. **Optimization Priority**:
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- C6 (57.2%): ✓ Already optimized with inline slots
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- C5 (28.5%): ✓ Already optimized with inline slots
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- C4 (14.3%): ← **Next optimization target**
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- C7 (0.0%): ✗ No presence in mixed workload
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4. **Engineering Trade-offs**:
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- C7 P2 would add complexity for 0% mixed-workload benefit
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- C4 redesign could improve 14.3% of operations
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- Consider phase-out of C7 optimization if isolated workloads don't justify it
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---
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## Conclusion
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**Phase 76-0 Complete**: C7 is definitively measured at 0.00% of Mixed SSOT operations.
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**Next Action**: Proceed to **Phase 76-1: C4 Analysis** to evaluate the largest remaining optimization opportunity (14.29% of total operations).
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**File**: `/tmp/phase76_0_c7_stats.log`
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**Date**: 2025-12-18
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**Status**: ✓ Decision gate established
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