feat(joinir): Phase 172 - Trim pattern JoinIR lowering implementation
Implement actual MIR generation for Trim pattern loops, enabling
LoopBodyLocal variables to work through bool carrier promotion.
## Implementation (pattern2_with_break.rs)
- emit_whitespace_check(): Generate OR chain for whitespace comparison
- extract_substring_args(): Extract s, start from substring call
- Initial carrier generation: ch0 = s.substring(start, start+1)
- Whitespace check: is_ch_match0 = (ch0 == " " || "\t" || "\n" || "\r")
- ConditionEnv integration: Register carrier for JoinIR condition
- Break condition replacement: !is_ch_match instead of original ch checks
## Architecture
- Host MIR: substring calls, OR chain evaluation, BoxCall
- JoinIR: Only sees bool carrier for break control
- No new JoinIR instructions added
## Documentation
- phase172-trim-lowering-impl.md: Design and implementation details
- loop_pattern_space.md: Analysis of all loop pattern combinations
Test: Trim loops compile and generate JoinIR successfully
Build: 0 errors, clean compilation
🤖 Generated with [Claude Code](https://claude.com/claude-code)
Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
5ba11468e4