b003bdf25b
Key updates: - Document MIR 26→15 instruction reduction plan (transitioning status) - Add Core-15 target instruction set in INSTRUCTION_SET.md - Save AI conference analyses validating Box Theory and 15-instruction design - Create MIR annotation system proposal for optimization hints - Update SKIP_PHASE_10_DECISION.md with LLVM direct migration rationale Technical insights: - RefNew/RefGet/RefSet can be eliminated through Box unification - GC/sync/async all achievable with 15 core instructions - BoxCall lowering can automatically insert GC barriers - 2-3x performance improvement expected with LLVM - Build time reduction 50%, binary size reduction 40% Status: Design complete, implementation pending
11 lines
311 B
Rust
11 lines
311 B
Rust
//! Host-callable externs for JIT-compiled code
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//!
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//! Phase 10_d: Provide thin bridges for Array/Map hot operations that
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//! JIT can call via symbol names. Lowering will resolve MIR ops into
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//! these externs once call emission is added.
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pub mod collections;
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pub mod handles;
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pub mod birth;
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pub mod runtime;
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