87fbe6b950
docs(phase29af): add P4 layout consistency instructions
2025-12-29 05:46:49 +09:00
bd4937d89d
phase29af(p2+p3): regression entrypoint + carrier layout ssot
2025-12-29 05:44:59 +09:00
9bc9454726
phase29af(p1): add boundary hygiene contract checks
2025-12-29 05:27:14 +09:00
19f2c6b7f6
phase29af(p0): pattern2 boundary hygiene ssot
2025-12-29 05:12:15 +09:00
62bd42b87f
docs(phase29ae): finalize regression pack SSOT
2025-12-29 03:59:25 +09:00
dd8c2709bd
fix(joinir): stabilize phase1883 latch/entry preds
2025-12-28 23:39:51 +09:00
d8786ebab9
phase29ad(p3): finalize pattern6/7 fixture naming ssot
2025-12-28 17:51:11 +09:00
432a8436c7
phase29ac(p3): keep Pattern7 contract freeze; add fixup OK fixture+smoke; closeout docs
2025-12-28 17:16:36 +09:00
a6c04217d0
docs(phase29ac): start P1 reverse scan
2025-12-28 16:54:55 +09:00
209b04d808
docs(phase29ab): closeout P1-P9
2025-12-28 16:36:15 +09:00
c397016ac7
docs(phase29ab): record P8 ok fixtures and queue closeout
2025-12-28 16:00:45 +09:00
5edda8a0c2
docs(phase29ab): record P7 pattern6 negative fixtures
2025-12-28 15:41:58 +09:00
7ae96fcc4c
docs(phase29ab): record P6 pattern6 contract freeze
2025-12-28 15:38:49 +09:00
bea2a8d9bb
phase29ab(p5): freeze pattern7 split-scan near-miss with fixture+smoke
2025-12-28 14:32:19 +09:00
7a790a27cb
docs(phase29ab): record P4 derived-slot realworld seg
2025-12-28 14:09:15 +09:00
280a5a8187
docs+api: finalize phase29ab P3 contract and update examples
2025-12-28 10:57:48 +09:00
6ba9d995d2
docs(phase29ab): record P2 seg trim fixture+smoke
2025-12-28 09:04:18 +09:00
506339def0
docs(phase29ab): record P1 pattern2 fixture+smoke
2025-12-28 07:19:23 +09:00
61a3384bd2
docs(phase29aa): mark P8 complete
2025-12-28 06:32:46 +09:00
6d17a0f988
docs(phase29aa): mark P7 complete and queue P8
2025-12-28 06:00:34 +09:00
d3cf73f2ae
phase29aa(p7): deterministic ReleaseStrong values ordering
2025-12-28 05:59:22 +09:00
ec1a84c465
docs(phase29aa): mark P6 complete and queue P7
2025-12-28 05:21:28 +09:00
120167bb6e
phase29aa(p6): intersect multi-pred return join state
2025-12-28 05:20:45 +09:00
c8c99174af
docs(phase29aa): queue P6 intersection join
2025-12-28 04:44:18 +09:00
02c01758b3
phase29aa(p5): multi-pred return join when states match
2025-12-28 04:43:19 +09:00
bf7b203586
phase29aa(p4): propagate rc state along jump chain to return
2025-12-28 01:56:36 +09:00
d70d9e3b89
docs(phase29aa): mark P3 complete and queue P4
2025-12-28 01:43:03 +09:00
94ad562aa5
Phase 29aa P3: Jump→Return single-pred rc propagation
2025-12-28 01:16:52 +09:00
7be0b0c28e
phase29aa: RcPlan + guard no cleanup on jump/branch
2025-12-27 16:09:26 +09:00
b6e80943a3
phase29aa(p1): rc insertion plan/apply refactor
2025-12-27 16:02:32 +09:00
d32b72653c
docs(phase29aa): mark P1 pending until code lands
2025-12-27 15:49:42 +09:00
91adbd0547
docs(now): mark phase29z P2 closeout
2025-12-27 15:41:46 +09:00
b895f67e07
docs(phase29aa): add P0 CFG-aware design and link from 29z
2025-12-27 15:38:18 +09:00
a916066631
phase29z(p2): return cleanup and null propagation doc alignment
2025-12-27 15:26:42 +09:00
084277ee18
docs(phase29z): P2 closeout markers and next steps
2025-12-27 15:21:40 +09:00
5a3d45ce53
phase29z(p1): handle explicit drop in rc insertion
2025-12-27 15:16:46 +09:00
977f105e4e
phase29z(p0): minimal RC insertion overwrite release
2025-12-27 15:03:05 +09:00
2223c1309b
docs(phase29z): Add RC insertion minimal instructions
2025-12-27 14:18:33 +09:00
292fb83dcb
docs(phase29y): Finalize P0 SSOT
2025-12-27 14:17:18 +09:00
9c6b725e3e
docs(phase29y): Add P0 docs-finalize instructions
2025-12-27 14:04:56 +09:00
60e3510b26
docs(phase287): Complete P9 closeout
2025-12-27 14:02:53 +09:00
25bd15a64c
docs(phase287): Add P9 closeout instructions
2025-12-27 13:57:33 +09:00
74c6df1acb
docs(phase287): Mark P7 complete, add P8 instructions
2025-12-27 13:39:04 +09:00
df4d0b1776
docs(phase287): Mark P6 complete, add P7 instructions
2025-12-27 13:26:33 +09:00
8d4472ddd3
docs(phase287): Mark P5 complete, add P6 instructions
2025-12-27 13:20:16 +09:00
ad5b6085c1
docs(phase287): Mark P4 complete, add P5 instructions
2025-12-27 12:50:17 +09:00
2f7061e2e5
docs(phase287): Mark P3 complete, add P4 instructions
2025-12-27 12:17:47 +09:00
fe895e8838
refactor(joinir): Phase 287 P2 - Modularize contract_checks (facade pattern)
...
- contract_checks.rs (846行) を facade 化
- 6モジュールへ分割（1 module = 1 contract）:
- terminator_targets.rs (208行) - Branch/Jump検証
- exit_bindings.rs (35行) - exit_bindings ↔ exit_phis
- carrier_inputs.rs (145行) - carrier_inputs完全性
- boundary_creation.rs (160行) - B1/C2不変条件
- entry_params.rs (317行) - Entry param一貫性
- mod.rs (30行) - Facade
- Total: 846 → 895行（+49行モジュール境界オーバーヘッド）
- 意味論不変: エラータグ/ヒント文すべて保存
- Fail-Fast遵守: silent fallback追加なし
- 検証: Build 0 errors / Pattern6 RC=9 / quick 154/154 PASS
🤖 Generated with [Claude Code](https://claude.com/claude-code )
Co-Authored-By: Claude Sonnet 4.5 <noreply@anthropic.com >
2025-12-27 11:05:40 +09:00
433e1d45c0
refactor(joinir): Phase 287 P0.1 - Move verification to debug_assertions
...
- Move verify_no_phi_dst_overwrite() to debug_assertions.rs
- Move verify_phi_inputs_defined() to debug_assertions.rs
- Move verify_joinir_contracts() to debug_assertions.rs
- Remove duplicate get_instruction_dst() from mod.rs
- mod.rs: 1,555 → ~1,380 lines (-176 lines)
- Semantic invariance: 154/154 smoke tests PASS, Pattern6 RC:9
Phase 287 P0: Big Files Refactoring (意味論不変)
🤖 Generated with [Claude Code](https://claude.com/claude-code )
Co-Authored-By: Claude Sonnet 4.5 <noreply@anthropic.com >
2025-12-27 10:10:59 +09:00
a04b48416e
fix(joinir): Phase 287 P2 - Pattern6 nested loop latch overwrite fix
...
Fix infinite loop in Pattern6 (nested loop minimal) caused by main→loop_step
overwriting k_inner_exit→loop_step latch values.
Root cause: JoinIR main entry block was incorrectly treated as BackEdge,
causing it to overwrite the correct latch incoming values set by the true
back edge (k_inner_exit → loop_step).
Solution:
- Restrict latch recording to TailCallKind::BackEdge only
- Treat only MAIN's entry block as entry-like (not loop_step's entry block)
- Add debug_assert! to detect double latch set in future
Refactoring:
- Extract latch recording to latch_incoming_recorder module (SSOT)
- Add boundary.loop_header_func_name for explicit header identification
- Strengthen tail_call_classifier with is_source_entry_like parameter
Tests: apps/tests/phase1883_nested_minimal.hako → RC:9 (was infinite loop)
Smoke: 154/154 PASS, no regressions
🤖 Generated with [Claude Code](https://claude.com/claude-code )
Co-Authored-By: Claude Sonnet 4.5 <noreply@anthropic.com >
2025-12-27 09:39:29 +09:00
