Commit Graph

12 Commits

Author SHA1 Message Date
46d47e2948 Tests(MIR): add lowering tests ensuring TypeOp for print(isType(...)) and print(obj.is(...)); note: cargo check passes, test harness currently blocked by CLI config fields unrelated to MIR changes. 2025-08-25 20:09:12 +09:00
0aef8d49a7 Phase 2: TypeOp変換の一本化(Optimizer安全ネット削除)\nPhase 3: 可視化/スナップショット基盤(--mir-verbose-effects, snapshot/compare/ci_check)\nDocs: Phase 1/2 完了マーク・利用方法追記 2025-08-24 01:58:41 +09:00
3c3dc86be0 feat: MIR builder TypeOp lowering for is/as methods and isType/asType functions
- Add early TypeOp lowering in build_expression for method-style is()/as()
- Add early TypeOp lowering in build_expression for function-style isType()/asType()
- Add special handling in build_print_statement for print(isType/asType(...))
- Fix MIR optimizer borrow checker issues and remove obsolete BoxFieldLoad
- Extract string literal helper supports both direct literals and StringBox wrappers
- Note: isType call generation still has issues (undefined SSA value in print)

🤖 Generated with Claude Code

Co-Authored-By: Claude <noreply@anthropic.com>
2025-08-24 00:05:12 +09:00
fffbac9aac feat: MIR TypeOp/WeakRef/Barrier PoC implementation
- Add TypeOpKind, WeakRefOp, BarrierOp enums for unified instructions
- Implement TypeOp instruction combining TypeCheck/Cast
- Implement WeakRef instruction combining WeakNew/WeakLoad
- Implement Barrier instruction combining BarrierRead/BarrierWrite
- Update VM to handle new unified instructions
- Update MIR printer for new instruction formats
- Add feature flags mir_typeop_poc and mir_refbarrier_unify_poc
- Maintain backward compatibility with legacy instructions

This is Phase 8.5 MIR instruction diet PoC implementation.

🤖 Generated with [Claude Code](https://claude.ai/code)

Co-Authored-By: Claude <noreply@anthropic.com>
2025-08-23 19:27:02 +09:00
bab57e7c07 🎉 feat: ChatGPT5による奇跡の全テスト修復完了!
- instance_v2移行で破綻していた440個のテストを30分で全修正
- git巻き戻しレベルの状況から完全復活
- 人間には不可能な速度での大規模整合性修正

🤖 Generated with [Claude Code](https://claude.ai/code)

Co-Authored-By: Claude <noreply@anthropic.com>
2025-08-20 04:45:26 +09:00
840c1b85ef feat: Fix VM SSA loop execution with proper phi node handling
Fixed infinite loop issue in VM by addressing phi node caching problem.
The phi node was caching the initial value and returning it for all
subsequent iterations, preventing loop variable updates.

Changes:
- Created vm_phi.rs module to separate loop execution logic (similar to mir/loop_builder.rs)
- Disabled phi node caching to ensure correct value selection each iteration
- Added LoopExecutor to track block transitions and handle phi nodes properly
- Fixed VM to correctly track previous_block for phi input selection

The VM now correctly executes SSA-form loops with proper variable updates:
- Loop counter increments correctly
- Phi nodes select the right input based on control flow
- Test case now completes successfully (i=1,2,3,4)

🤖 Generated with [Claude Code](https://claude.ai/code)

Co-Authored-By: Claude <noreply@anthropic.com>
2025-08-18 23:36:40 +09:00
bec0e9bc92 revert: 古いプラグインシステム実装前の状態に巻き戻し
- ソースコードをcommit 3f7d71fの状態に復元(古いプラグインシステム実装前)
- docsフォルダは最新の状態を維持(BID-FFI設計ドキュメント含む)
- nyashバイナリの基本動作確認済み
- BID-FFIシステムをクリーンに再実装する準備完了

🤖 Generated with [Claude Code](https://claude.ai/code)

Co-Authored-By: Claude <noreply@anthropic.com>
2025-08-18 08:34:19 +09:00
bb3f2e8032 feat: Complete Phase 3 of MIR 35→26 reduction - optimization pass migration
- Remove old instructions from VM/WASM backends (UnaryOp, Print, Load/Store, RefGet/RefSet)
- Add comprehensive MIR optimizer with Effect System based optimizations
- Implement dead code elimination, CSE, pure instruction reordering
- Add intrinsic function support in VM backend
- Update backends to use new BoxFieldLoad/Store and Call intrinsics

🤖 Generated with [Claude Code](https://claude.ai/code)

Co-Authored-By: Claude <noreply@anthropic.com>
2025-08-17 12:27:12 +09:00
f5f85ef175 Complete Phase 8.5A: MIR 25-instruction hierarchical implementation with working tests and demo
Co-authored-by: moe-charm <217100418+moe-charm@users.noreply.github.com>
2025-08-14 02:46:08 +00:00
525747d2b3 Implement Phase 8.5A: Core 25-instruction MIR specification with ownership verification
Co-authored-by: moe-charm <217100418+moe-charm@users.noreply.github.com>
2025-08-14 02:39:04 +00:00
d3a85b2305 Implement Phase 5: Control flow & exceptions in MIR/VM - Core functionality complete
Co-authored-by: moe-charm <217100418+moe-charm@users.noreply.github.com>
2025-08-13 06:23:28 +00:00
774e0bb241 🚀 MIR Stage 1 Basic Infrastructure Complete - 20 Instructions + SSA + Effects
Co-authored-by: moe-charm <217100418+moe-charm@users.noreply.github.com>
2025-08-12 11:33:48 +00:00