📚 Phase 11 documentation: Everything is Box × MIR15 revolution
Key updates: - Document MIR 26→15 instruction reduction plan (transitioning status) - Add Core-15 target instruction set in INSTRUCTION_SET.md - Save AI conference analyses validating Box Theory and 15-instruction design - Create MIR annotation system proposal for optimization hints - Update SKIP_PHASE_10_DECISION.md with LLVM direct migration rationale Technical insights: - RefNew/RefGet/RefSet can be eliminated through Box unification - GC/sync/async all achievable with 15 core instructions - BoxCall lowering can automatically insert GC barriers - 2-3x performance improvement expected with LLVM - Build time reduction 50%, binary size reduction 40% Status: Design complete, implementation pending
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@ -119,7 +119,9 @@ impl MirBuilder {
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let exit_block = self.block_gen.next();
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// Set up exception handler for the try block (before we enter it)
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if let Some(catch_clause) = catch_clauses.first() {
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if std::env::var("NYASH_BUILDER_DISABLE_TRYCATCH").ok().as_deref() == Some("1") {
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// Fallback: build try body only
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} else if let Some(catch_clause) = catch_clauses.first() {
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let exception_value = self.value_gen.next();
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// Register catch handler for exceptions that may occur in try block
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@ -152,6 +154,7 @@ impl MirBuilder {
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self.start_new_block(catch_block)?;
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// Handle catch clause
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if std::env::var("NYASH_BUILDER_DISABLE_TRYCATCH").ok().as_deref() != Some("1") {
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if let Some(catch_clause) = catch_clauses.first() {
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// Build catch body
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let catch_ast = ASTNode::Program {
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@ -159,7 +162,7 @@ impl MirBuilder {
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span: crate::ast::Span::unknown(),
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};
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self.build_expression(catch_ast)?;
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}
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}}
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// Catch completion - jump to finally or exit (if not already terminated)
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if !self.is_current_block_terminated() {
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