refactor(llvm): Complete Resolver pattern implementation across all instructions

Major structural improvement driven by ChatGPT 5 Pro analysis:
- Replace all direct vmap access with Resolver API calls
- Add proper cursor/bb_map/preds/block_end_values to all instruction handlers
- Ensure dominance safety by localizing values through Resolver
- Fix parameter passing in invoke/fields/extern handlers

Key changes:
- boxcall: Use resolver.resolve_i64/ptr instead of direct vmap access
- strings: Remove unused recv_v parameter, use Resolver throughout
- invoke: Add missing context parameters for proper PHI handling
- fields: Add resolver and block context parameters
- flow/arith/maps: Consistent Resolver usage pattern

This addresses the "structural invariant" requirements:
1. All value fetching goes through Resolver (no direct vmap.get)
2. Localization happens at BB boundaries via Resolver
3. Better preparation for PHI-only-in-dispatch pattern

Next: Consider boxing excessive parameters (15+ args in some functions)

🤖 Generated with [Claude Code](https://claude.ai/code)

Co-Authored-By: Claude <noreply@anthropic.com>

src/backend/llvm/compiler/codegen/mod.rs

@@ -356,7 +356,20 @@ impl LLVMCompiler {
                         if let Some(d) = dst { defined_in_block.insert(*d); }
                     },
                     MirInstruction::UnaryOp { dst, op, operand } => {
-                        instructions::lower_unary(&codegen, &mut cursor, *bid, &mut vmap, *dst, op, operand)?;
+                        instructions::lower_unary(
+                            &codegen,
+                            &mut cursor,
+                            &mut resolver,
+                            *bid,
+                            func,
+                            &mut vmap,
+                            *dst,
+                            op,
+                            operand,
+                            &bb_map,
+                            &preds,
+                            &block_end_values,
+                        )?;
                         defined_in_block.insert(*dst);
                     },
                     MirInstruction::BinOp { dst, op, lhs, rhs } => {
@@ -407,7 +420,18 @@ impl LLVMCompiler {
                 cursor.at_end(*bid, bb);
                 match term {
                     MirInstruction::Return { value } => {
-                        instructions::emit_return(&codegen, &mut cursor, *bid, func, &vmap, value)?;
+                        instructions::emit_return(
+                            &codegen,
+                            &mut cursor,
+                            &mut resolver,
+                            *bid,
+                            func,
+                            &vmap,
+                            value,
+                            &bb_map,
+                            &preds,
+                            &block_end_values,
+                        )?;
                     }
                     MirInstruction::Jump { target } => {
                         // LoopForm simple body→dispatch wiring: if this block is a loop body
@@ -480,6 +504,7 @@ impl LLVMCompiler {
                                 handled_by_loopform = instructions::lower_while_loopform(
                                     &codegen,
                                     &mut cursor,
+                                    &mut resolver,
                                     func,
                                     llvm_func,
                                     condition,
@@ -491,6 +516,8 @@ impl LLVMCompiler {
                                     after_sel,
                                     &bb_map,
                                     &vmap,
+                                    &preds,
+                                    &block_end_values,
                                     &mut loopform_registry,
                                     &mut loopform_body_to_header,
                                 )?;