feat(llvm): Phase 131-11-H/12 - ループキャリアPHI型修正 & vmap snapshot SSOT
## Phase 131-11-H: ループキャリアPHI型修正 - PHI生成時に初期値(entry block)の型のみ使用 - backedge の値を型推論に使わない(循環依存回避) - NYASH_CARRIER_PHI_DEBUG=1 でトレース ## Phase 131-12-P0: def_blocks 登録 & STRICT エラー化 - safe_vmap_write() で PHI 上書き保護 - resolver miss を STRICT でエラー化(フォールバック 0 禁止) - def_blocks 自動登録 ## Phase 131-12-P1: vmap_cur スナップショット実装 - DeferredTerminator 構造体(block, term_ops, vmap_snapshot) - Pass A で vmap_cur をスナップショット - Pass C でスナップショット復元(try-finally) - STRICT モード assert ## 結果 - ✅ MIR PHI型: Integer(正しい) - ✅ VM: Result: 3 - ✅ vmap snapshot 機構: 動作確認 - ⚠️ LLVM: Result: 0(別のバグ、次Phase で調査) 🤖 Generated with [Claude Code](https://claude.com/claude-code) Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
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@ -6,6 +6,7 @@ Critical for SSA form - handles value merging from different control flow paths
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import llvmlite.ir as ir
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from phi_wiring import phi_at_block_head
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from typing import Dict, List, Tuple, Optional
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from utils.values import safe_vmap_write
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def lower_phi(
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builder: ir.IRBuilder,
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@ -131,6 +132,18 @@ def lower_phi(
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# Store PHI result
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vmap[dst_vid] = phi
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# Register PHI definition in def_blocks (critical for resolver dominance tracking)
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if resolver is not None and hasattr(resolver, 'def_blocks') and cur_bid is not None:
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resolver.def_blocks.setdefault(dst_vid, set()).add(cur_bid)
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import os
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if os.environ.get('NYASH_LLVM_PHI_DEBUG') == '1':
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try:
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from trace import phi as trace_phi_debug
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trace_phi_debug(f"[PHI_DEBUG] Registered dst_vid={dst_vid} in def_blocks for block={cur_bid}")
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except Exception:
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pass
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# Strict mode: fail fast on synthesized zeros (indicates incomplete incoming or dominance issue)
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import os
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if used_default_zero and os.environ.get('NYASH_LLVM_PHI_STRICT') == '1':
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