llvm: unify lowering via Resolver and Cursor; remove non-sealed PHI wiring; apply Resolver to extern/call/boxcall/arrays/maps/mem; add llvmlite harness docs; add LLVM layer overview; add LoopForm preheader

src/llvm_py/instructions/branch.py

@@ -0,0 +1,50 @@
+"""
+Branch instruction lowering
+Conditional branch based on condition value
+"""
+
+import llvmlite.ir as ir
+from typing import Dict
+
+def lower_branch(
+    builder: ir.IRBuilder,
+    cond_vid: int,
+    then_bid: int,
+    else_bid: int,
+    vmap: Dict[int, ir.Value],
+    bb_map: Dict[int, ir.Block]
+) -> None:
+    """
+    Lower MIR Branch instruction
+    
+    Args:
+        builder: Current LLVM IR builder
+        cond_vid: Condition value ID
+        then_bid: Then block ID
+        else_bid: Else block ID
+        vmap: Value map
+        bb_map: Block map
+    """
+    # Get condition value
+    cond = vmap.get(cond_vid)
+    if not cond:
+        # Default to false if missing
+        cond = ir.Constant(ir.IntType(1), 0)
+    
+    # Convert to i1 if needed
+    if hasattr(cond, 'type'):
+        if cond.type == ir.IntType(64):
+            # i64 to i1: compare != 0
+            zero = ir.Constant(ir.IntType(64), 0)
+            cond = builder.icmp_unsigned('!=', cond, zero, name="cond_i1")
+        elif cond.type == ir.IntType(8).as_pointer():
+            # Pointer to i1: compare != null
+            null = ir.Constant(cond.type, None)
+            cond = builder.icmp_unsigned('!=', cond, null, name="cond_p1")
+    
+    # Get target blocks
+    then_bb = bb_map.get(then_bid)
+    else_bb = bb_map.get(else_bid)
+    
+    if then_bb and else_bb:
+        builder.cbranch(cond, then_bb, else_bb)