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hakorune/docs/reference/mir/INSTRUCTION_SET.md

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📚 Phase 11 documentation: Everything is Box × MIR15 revolution Key updates: - Document MIR 26→15 instruction reduction plan (transitioning status) - Add Core-15 target instruction set in INSTRUCTION_SET.md - Save AI conference analyses validating Box Theory and 15-instruction design - Create MIR annotation system proposal for optimization hints - Update SKIP_PHASE_10_DECISION.md with LLVM direct migration rationale Technical insights: - RefNew/RefGet/RefSet can be eliminated through Box unification - GC/sync/async all achievable with 15 core instructions - BoxCall lowering can automatically insert GC barriers - 2-3x performance improvement expected with LLVM - Build time reduction 50%, binary size reduction 40% Status: Design complete, implementation pending
2025-08-31 03:03:04 +09:00
# Nyash MIR Instruction Set (Canonical 26 → migrating to Core-15)
Phase 9.78h: VM BinOp and/or short-circuit + BoxRef<Integer> arithmetic; add diagnostic hooks. Update CURRENT_TASK with progress and VM path-tracing TODO. Align docs: MIR26 canonical spec and phase docs.
2025-08-26 00:06:35 +09:00
📚 Phase 11 documentation: Everything is Box × MIR15 revolution Key updates: - Document MIR 26→15 instruction reduction plan (transitioning status) - Add Core-15 target instruction set in INSTRUCTION_SET.md - Save AI conference analyses validating Box Theory and 15-instruction design - Create MIR annotation system proposal for optimization hints - Update SKIP_PHASE_10_DECISION.md with LLVM direct migration rationale Technical insights: - RefNew/RefGet/RefSet can be eliminated through Box unification - GC/sync/async all achievable with 15 core instructions - BoxCall lowering can automatically insert GC barriers - 2-3x performance improvement expected with LLVM - Build time reduction 50%, binary size reduction 40% Status: Design complete, implementation pending
2025-08-31 03:03:04 +09:00
Status: Canonical (Source of Truth) — transitioning
Phase 9.78h: VM BinOp and/or short-circuit + BoxRef<Integer> arithmetic; add diagnostic hooks. Update CURRENT_TASK with progress and VM path-tracing TODO. Align docs: MIR26 canonical spec and phase docs.
2025-08-26 00:06:35 +09:00
Last Updated: 2025-08-25
📚 Phase 11 documentation: Everything is Box × MIR15 revolution Key updates: - Document MIR 26→15 instruction reduction plan (transitioning status) - Add Core-15 target instruction set in INSTRUCTION_SET.md - Save AI conference analyses validating Box Theory and 15-instruction design - Create MIR annotation system proposal for optimization hints - Update SKIP_PHASE_10_DECISION.md with LLVM direct migration rationale Technical insights: - RefNew/RefGet/RefSet can be eliminated through Box unification - GC/sync/async all achievable with 15 core instructions - BoxCall lowering can automatically insert GC barriers - 2-3x performance improvement expected with LLVM - Build time reduction 50%, binary size reduction 40% Status: Design complete, implementation pending
2025-08-31 03:03:04 +09:00
この文書はNyashのMIR命令セットの唯一の参照（現状は26命令）だよ。Core-15 への段階移行を進めており、安定次第この文書を15命令へ更新し、テスト固定数も切り替える（移行中は26を維持）。
Phase 9.78h: VM BinOp and/or short-circuit + BoxRef<Integer> arithmetic; add diagnostic hooks. Update CURRENT_TASK with progress and VM path-tracing TODO. Align docs: MIR26 canonical spec and phase docs.
2025-08-26 00:06:35 +09:00
📚 Phase 11 documentation: Everything is Box × MIR15 revolution Key updates: - Document MIR 26→15 instruction reduction plan (transitioning status) - Add Core-15 target instruction set in INSTRUCTION_SET.md - Save AI conference analyses validating Box Theory and 15-instruction design - Create MIR annotation system proposal for optimization hints - Update SKIP_PHASE_10_DECISION.md with LLVM direct migration rationale Technical insights: - RefNew/RefGet/RefSet can be eliminated through Box unification - GC/sync/async all achievable with 15 core instructions - BoxCall lowering can automatically insert GC barriers - 2-3x performance improvement expected with LLVM - Build time reduction 50%, binary size reduction 40% Status: Design complete, implementation pending
2025-08-31 03:03:04 +09:00
注意: Debug/Nop/Safepointはビルドモードでの降格用メタ命令であり、コア命令数には数えない。
Transition Note
- Builder/Rewrite/JIT は既に以下の統合を段階適用中
- TypeCheck/Cast → TypeOp
- WeakNew/WeakLoad → WeakRef
- BarrierRead/BarrierWrite → Barrier
- Print → ExternCall(env.console.log)（Deprecated）
📚 Reorganize CLAUDE.md: slim down from 916 to 395 lines with proper doc links - Keep essential information within 500 lines (now 395 lines) - Maintain important syntax examples and development principles - Move detailed information to appropriate docs files: - Development practices → docs/guides/development-practices.md - Testing guide → docs/guides/testing-guide.md - Claude issues → docs/tools/claude-issues.md - Add proper links to all referenced documentation - Balance between minimal entry point and practical usability
2025-08-31 06:22:48 +09:00
- PluginInvoke → BoxCall（Deprecated; 名前/スロット解決はBoxCall側で処理）
📚 Phase 11 documentation: Everything is Box × MIR15 revolution Key updates: - Document MIR 26→15 instruction reduction plan (transitioning status) - Add Core-15 target instruction set in INSTRUCTION_SET.md - Save AI conference analyses validating Box Theory and 15-instruction design - Create MIR annotation system proposal for optimization hints - Update SKIP_PHASE_10_DECISION.md with LLVM direct migration rationale Technical insights: - RefNew/RefGet/RefSet can be eliminated through Box unification - GC/sync/async all achievable with 15 core instructions - BoxCall lowering can automatically insert GC barriers - 2-3x performance improvement expected with LLVM - Build time reduction 50%, binary size reduction 40% Status: Design complete, implementation pending
2025-08-31 03:03:04 +09:00
- VM/JIT の代表的な Core-15 カバー手順は `docs/reference/mir/MIR15_COVERAGE_CHECKLIST.md` を参照。
- Core-15 安定後に本ドキュメントの「Core Instructions」を15命令へ更新し、マッピング表を併記する。
Phase 9.78h: VM BinOp and/or short-circuit + BoxRef<Integer> arithmetic; add diagnostic hooks. Update CURRENT_TASK with progress and VM path-tracing TODO. Align docs: MIR26 canonical spec and phase docs.
2025-08-26 00:06:35 +09:00
## Core Instructions（26）
- Const
- Copy
- Load
- Store
- UnaryOp
- BinOp
- Compare
- Jump
- Branch
- Phi
- Return
- Call
- ExternCall
- BoxCall
phase_9_79b_1: Add Unified Registry IDs + Builder Slotting\n- MIR BoxCall carries optional method_id (slot)\n- Slot registry with universal slots [0..3]\n- Builder resolves method_id when receiver type known\n- Printer shows method_id; backends updated\n- Update CURRENT_TASK + MIR spec note
2025-08-26 20:48:48 +09:00
- Note: BoxCall carries optional `method_id` (numeric slot) when the builder can resolve the receiver type; otherwise falls back to name-only late bind. Universal methods use reserved slots: 0=toString, 1=type, 2=equals, 3=clone.
Phase 9.78h: VM BinOp and/or short-circuit + BoxRef<Integer> arithmetic; add diagnostic hooks. Update CURRENT_TASK with progress and VM path-tracing TODO. Align docs: MIR26 canonical spec and phase docs.
2025-08-26 00:06:35 +09:00
- NewBox
- ArrayGet
- ArraySet
- RefNew
- RefGet
- RefSet
- Await
📚 Phase 11 documentation: Everything is Box × MIR15 revolution Key updates: - Document MIR 26→15 instruction reduction plan (transitioning status) - Add Core-15 target instruction set in INSTRUCTION_SET.md - Save AI conference analyses validating Box Theory and 15-instruction design - Create MIR annotation system proposal for optimization hints - Update SKIP_PHASE_10_DECISION.md with LLVM direct migration rationale Technical insights: - RefNew/RefGet/RefSet can be eliminated through Box unification - GC/sync/async all achievable with 15 core instructions - BoxCall lowering can automatically insert GC barriers - 2-3x performance improvement expected with LLVM - Build time reduction 50%, binary size reduction 40% Status: Design complete, implementation pending
2025-08-31 03:03:04 +09:00
- Print（Deprecated: ビルダーは発行しない。代わりに `ExternCall env.console.log` を使用）
Phase 9.78h: VM BinOp and/or short-circuit + BoxRef<Integer> arithmetic; add diagnostic hooks. Update CURRENT_TASK with progress and VM path-tracing TODO. Align docs: MIR26 canonical spec and phase docs.
2025-08-26 00:06:35 +09:00
- TypeOp（TypeCheck/Cast統合）
- WeakRef（WeakNew/WeakLoad統合）
- Barrier（Read/Write統合）
📚 Phase 11 documentation: Everything is Box × MIR15 revolution Key updates: - Document MIR 26→15 instruction reduction plan (transitioning status) - Add Core-15 target instruction set in INSTRUCTION_SET.md - Save AI conference analyses validating Box Theory and 15-instruction design - Create MIR annotation system proposal for optimization hints - Update SKIP_PHASE_10_DECISION.md with LLVM direct migration rationale Technical insights: - RefNew/RefGet/RefSet can be eliminated through Box unification - GC/sync/async all achievable with 15 core instructions - BoxCall lowering can automatically insert GC barriers - 2-3x performance improvement expected with LLVM - Build time reduction 50%, binary size reduction 40% Status: Design complete, implementation pending
2025-08-31 03:03:04 +09:00
## Core-15（Target; 移行中の最小コア）
- 基本演算(5): Const, UnaryOp, BinOp, Compare, TypeOp
- メモリ(2): Load, Store
- 制御(4): Branch, Jump, Return, Phi
- Box(3): NewBox, BoxCall, PluginInvoke
- 配列(2): ArrayGet, ArraySet
- 外部(1): ExternCall
Notes
- Print/Debug/Safepointはメタ/Extern化（Print→ExternCall）。
- WeakRef/Barrier は統合済み（旧WeakNew/WeakLoad/BarrierRead/WriteはRewriteで互換）。
📚 Reorganize CLAUDE.md: slim down from 916 to 395 lines with proper doc links - Keep essential information within 500 lines (now 395 lines) - Maintain important syntax examples and development principles - Move detailed information to appropriate docs files: - Development practices → docs/guides/development-practices.md - Testing guide → docs/guides/testing-guide.md - Claude issues → docs/tools/claude-issues.md - Add proper links to all referenced documentation - Balance between minimal entry point and practical usability
2025-08-31 06:22:48 +09:00
- Call は BoxCall へ集約（PluginInvokeはDeprecated）。
📚 Phase 11 documentation: Everything is Box × MIR15 revolution Key updates: - Document MIR 26→15 instruction reduction plan (transitioning status) - Add Core-15 target instruction set in INSTRUCTION_SET.md - Save AI conference analyses validating Box Theory and 15-instruction design - Create MIR annotation system proposal for optimization hints - Update SKIP_PHASE_10_DECISION.md with LLVM direct migration rationale Technical insights: - RefNew/RefGet/RefSet can be eliminated through Box unification - GC/sync/async all achievable with 15 core instructions - BoxCall lowering can automatically insert GC barriers - 2-3x performance improvement expected with LLVM - Build time reduction 50%, binary size reduction 40% Status: Design complete, implementation pending
2025-08-31 03:03:04 +09:00
Phase 9.78h: VM BinOp and/or short-circuit + BoxRef<Integer> arithmetic; add diagnostic hooks. Update CURRENT_TASK with progress and VM path-tracing TODO. Align docs: MIR26 canonical spec and phase docs.
2025-08-26 00:06:35 +09:00
## Meta (降格対象; カウント外)
- Debug
- Nop
- Safepoint
## 同期ルール
- 命令の追加/削除/統合は、まずこの文書を更新し、次に実装（列挙/Printer/Verifier/Optimizer/VM）を同期。最後に「総数=26」テストを更新する。
- 実装が26を外れた場合はCIを赤にする（設計の合意なく増減させないため）。
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