|
|
89a9212700
|
Phase 83-1 + Allocator Comparison: Switch dispatch fixed (NO-GO +0.32%), PROFILE correction, SCORECARD update
Key changes:
- Phase 83-1: Switch dispatch fixed mode (tiny_inline_slots_switch_dispatch_fixed_box) - NO-GO (marginal +0.32%, branch reduction negligible)
Reason: lazy-init pattern already optimal, Phase 78-1 pattern shows diminishing returns
- Allocator comparison baseline update (10-run SSOT, WS=400, ITERS=20M):
tcmalloc: 115.26M (92.33% of mimalloc)
jemalloc: 97.39M (77.96% of mimalloc)
system: 85.20M (68.24% of mimalloc)
mimalloc: 124.82M (baseline)
- hakmem PROFILE correction: scripts/run_mixed_10_cleanenv.sh + run_allocator_quick_matrix.sh
PROFILE explicitly set to MIXED_TINYV3_C7_SAFE for hakmem measurements
Result: baseline stabilized to 55.53M (44.46% of mimalloc)
Previous unstable measurement (35.57M) was due to profile leak
- Documentation:
* PERFORMANCE_TARGETS_SCORECARD.md: Reference allocators + M1/M2 milestone status
* PHASE83_1_SWITCH_DISPATCH_FIXED_RESULTS.md: Phase 83-1 analysis (NO-GO)
* ALLOCATOR_COMPARISON_QUICK_RUNBOOK.md: Quick comparison procedure
* ALLOCATOR_COMPARISON_SSOT.md: Detailed SSOT methodology
- M2 milestone status: 44.46% (target 55%, gap -10.54pp) - structural improvements needed
🤖 Generated with Claude Code
Co-Authored-By: Claude Sonnet 4.5 <noreply@anthropic.com>
|
2025-12-18 18:50:00 +09:00 |
|
|
|
0009ce13b3
|
Phase 75-1: C6-only Inline Slots (P2) - GO (+2.87%)
Modular implementation of hot-class inline slots optimization:
- Created 5 new boxes: env_box, tls_box, fast_path_api, integration_box, test_script
- Single decision point at TLS init (ENV gate: HAKMEM_TINY_C6_INLINE_SLOTS=0/1)
- Integration: 2 minimal boundary points (alloc/free paths for C6 class)
- Default OFF: zero overhead when disabled (full backward compatibility)
Results (10-run Mixed SSOT, WS=400):
- Baseline (C6 inline OFF): 44.24 M ops/s
- Treatment (C6 inline ON): 45.51 M ops/s
- Delta: +1.27 M ops/s (+2.87%)
Status: ✅ GO - Strong improvement via C6 ring buffer fast-path
Mechanism: Branch elimination on unified_cache_push/pop for C6 allocations
Next: Phase 75-2 (add C5 inline slots, target 85% C4-C7 coverage)
🤖 Generated with [Claude Code](https://claude.com/claude-code)
Co-Authored-By: Claude Haiku 4.5 <noreply@anthropic.com>
|
2025-12-18 08:22:09 +09:00 |
|
