Phase 62: C7 ULTRA Hotpath Optimization - Planning & Profiling Analysis
Complete planning for Phase 62 based on runtime profiling of Phase 59b baseline. Key Findings (200M ops Mixed benchmark): - tiny_c7_ultra_alloc: 5.18% (new primary target, 5x larger than Phase 61) - tiny_region_id_write_header: 3.82% (reconfirmed, Phase 61 showed 2.32%) - Allocation-specific hot path: 12.37% (C7 + header + cache) Phase 62 Recommendation: Option A (C7 ULTRA Inline + IPC Analysis) - Expected gain: +1-3% (higher absolute margin than Phases 46A/61) - Risk level: Medium (layout tax precedent from Phase 46A -0.68%, Phase 43 -1.18%) - Approach: Deep profiling → ASM inspection → A/B test with ENV gate Alternative Options: - Option B: tiny_region_id_write_header (3.82%, higher risk) - Option C: Algorithmic redesign (post-50% milestone) Box Theory Compliance: - Single conversion point: tiny_c7_ultra_alloc() boundary - Reversible: ENV gate HAKMEM_TINY_C7_ULTRA_INLINE_OPT (0/1) - No side effects: Pure dependency chain reordering Timeline: Single phase, 4-6 hours (profile + ASM + test) Documentation: - PHASE62_NEXT_TARGET_ANALYSIS.md: Complete planning document with profiling data - CURRENT_TASK.md: Updated next phase guidance Profiling tools prepared: - perf record with extended events (cycles, cache-misses, branch-misses) - ASM inspection methodology documented - A/B test threshold: ±0.5% (micro-scale) 🤖 Generated with Claude Code Co-Authored-By: Claude Haiku 4.5 <noreply@anthropic.com>
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## 3) 次の指示書
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**Phase 62: 次（TBD）**
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**Phase 62: C7 ULTRA Hotpath Optimization - Planning Complete**
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- Phase 61 が NEUTRAL (+0.31%) だったため、次のターゲットを探索する
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- Runtime profiling で Top 50 のホット関数を確認（Phase 61: `tiny_region_id_write_header` 2.32%, `tiny_c7_ultra_alloc` 1.90%）
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- 候補: TLS prefetch optimization, refill batch size tuning, IPC profiling
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Phase 59b・61 完了後、runtime profiling により次のターゲット特定:
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- **新 Profile**: 200M ops Mixed benchmark (Speed-first mode)
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- tiny_c7_ultra_alloc: **5.18%** (2.41% self + multi-stack overhead)
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- tiny_region_id_write_header: **3.82%** (2.72% + 1.10%)
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- unified_cache_push: 1.37% (Phase 46A already pursued)
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- **Phase 62 推奨**: C7 ULTRA Inline + IPC Analysis
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- Option A: tiny_c7_ultra_alloc dependency chain reordering (+1-3% expected)
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- Option B: tiny_region_id_write_header reordering (+0.5-1.5%, higher risk)
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- Option C: Algorithmic redesign (post-50% milestone)
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詳細: `docs/analysis/PHASE62_NEXT_TARGET_ANALYSIS.md`（完了、ready for implementation）
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**Phase 61: 完了（NEUTRAL +0.31%, research box）**
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docs/analysis/PHASE62_NEXT_TARGET_ANALYSIS.md
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# Phase 62: Allocation Hotpath Optimization - Target Analysis
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**Date**: 2025-12-17
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**Status**: Planning Phase
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**Baseline**: 48.34% of mimalloc (Phase 59b Speed-first)
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---
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## Executive Summary
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Runtime profiling (Phase 59b Speed-first profile) reveals that after Phases 59-61 micro-optimization attempts, the next highest-value targets are:
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1. **tiny_c7_ultra_alloc: 5.18%** (new primary target)
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2. **tiny_region_id_write_header: 3.82%** (reconfirmed hot)
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3. **unified_cache_push: 1.37%** (already optimized in Phase 46A)
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Phase 62 targets `tiny_c7_ultra_alloc` dependency chain optimization with potential +1-3% gain.
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---
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## Profiling Results (200M ops Mixed benchmark)
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### Top Allocation Functions
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```
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Function | Self % | Stack % | Status
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----------------------------------|--------|----------|------------------
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malloc (wrapper) | 27.17% | ~60% | Core loop
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free (wrapper) | 25.95% | ~60% | Core loop
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main (benchmark loop) | 26.78% | ~60% | Core loop
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tiny_c7_ultra_alloc | 2.41% | 5.18% | NEW TARGET
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tiny_region_id_write_header | 2.72% | 3.82% | Phase 61 confirmed
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unified_cache_push | 1.37% | 1.37% | Phase 46A (no-go)
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tiny_c7_ultra_free | 0.56% | 0.56% | Lower priority
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```
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**Note**: Stack % represents cumulative overhead from multiple call stacks
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### Key Findings
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1. **Allocation Specific Hot Path**: 12.37% (C7 ultra + region write + cache)
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2. **Core Allocator**: 79.9% (malloc + free + main loop interactions)
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3. **Profiling Confidence**: 376 samples, clear hot path, low noise
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---
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## Phase 62 Options
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### Option A: C7 ULTRA Hotpath (5.18% - PRIMARY CANDIDATE)
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**Opportunities**:
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- **A1: Inline Decision Path** - Ensure `tiny_c7_ultra_alloc` always inlined
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- **A2: TLS Prefetch** - Speculatively load C7 metadata structure
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- **A3: Dependency Chain Reduction** - Reorder operations for parallelism
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- **A4: Carve Batch Optimization** - Pre-carve slabs to reduce refill calls
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**Expected Gain**: +1-3% (5.18% of addressable performance)
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**Risk Level**: Medium
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- Precedent: Phase 46A similar optimization (-0.68% from layout tax)
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- Phase 43: Branch elimination (-1.18% regression)
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- But: 5x larger than Phase 46A target (higher absolute gain margin)
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**Rationale**:
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- C7 ULTRA already optimized in free (Phase 7+), alloc side underexplored
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- No successful alloc-side structural optimization since Phase 39 (+1.98% gate prune)
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- This is not micro-architecture bound (unlike Phase 46A store-ordering)
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---
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### Option B: tiny_region_id_write_header (3.82% - SECONDARY)
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**Opportunities**:
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- **B1: Dependency Chain Reorder** - Schedule non-dependent operations earlier
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- **B2: Condition Consolidation** - Reduce branch count
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- **B3: Store Bypass** - Avoid load-after-store stalls
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**Expected Gain**: +0.5-1.5%
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**Risk Level**: High
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- Phase 43: Header write optimization (-1.18%)
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- Phase 46A: always_inline (-0.68%)
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- Layout tax is real and measurable
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**Decision**: Secondary option; pursue only if Option A fails
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---
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### Option C: Algorithmic Redesign (VERY HIGH IMPACT, VERY HIGH COST)
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**Examples**:
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- Segment pre-allocation vs demand-based
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- Free-side batching (coalesce multiple frees)
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- Static route caching (trade memory for latency)
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**Expected Gain**: +3-8% (affects 79.9% core functions)
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**Risk**: Very high (requires major refactoring, extensive testing)
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**Decision**: Post-50% milestone option; requires strategic decision
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---
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## Phase 62A Recommendation: C7 ULTRA Inline + IPC Analysis
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### Implementation Plan
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**Step 1: Deep Profiling** (1-2 hours)
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```bash
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perf record -F 99 -g -e cycles:P,cache-misses,branch-misses,stalled-cycles-frontend \
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-- ./bench_random_mixed_hakmem_minimal 200000000 400 1
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perf report --stdio | grep -A 20 "tiny_c7_ultra_alloc"
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```
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**Step 2: ASM Inspection** (1 hour)
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- objdump -d on tiny_c7_ultra_alloc
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- Identify dependency chains (load-use, store-use distances)
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- Map to CPU latencies (L1: 4 cycles, L2: 10, L3: 40-75)
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- Identify stores that can be deferred/reordered
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**Step 3: A/B Test** (2-3 hours)
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- Create `HAKMEM_TINY_C7_ULTRA_INLINE_OPT` ENV gate
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- Implement dependency chain reordering (if identified)
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- Run 10-run Mixed benchmark
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- Measure +/- threshold: ±0.5% (micro-scale)
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**Step 4: Decision**
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- +0.5% or higher → GO (adopt as default)
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- ±0.5% → NEUTRAL (keep as research box)
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- -0.5% or lower → NO-GO (revert, document)
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---
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## Alternative: Quick Validation (if time-limited)
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If deep optimization is not feasible, proceed with:
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1. **Phase 62B: Static Routing Cache** - Pre-compute route decisions for each class
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- Phase 45 suggested +0.5-1.0% from TLS prefetch
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- Lower risk than C7 modification
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2. **Phase 62C: Carve Batch Study** - Analyze carve operation frequency
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- May identify batching opportunity with minimal code changes
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---
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## Box Theory Compliance
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- **Single Conversion Point**: C7 ultra path has clear entry point
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- **Clear Boundary**: tiny_c7_ultra_alloc() function boundary
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- **Reversible**: ENV gate (`HAKMEM_TINY_C7_ULTRA_INLINE_OPT=0/1`)
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- **No Side Effects**: Pure optimization, no new data structures
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- **Performance**: Expected +1-3% (TBD via A/B test)
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---
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## Success Criteria
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| Metric | Target | Status |
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|--------|--------|--------|
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| M1 (50%) | 50.0% | 48.34% (gap -1.66%) |
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| Throughput improvement | +1-3% | TBD |
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| Variance (CV) | <2.5% | Current 2.52% ✓ |
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| Memory efficiency | <35MB RSS | Current 33MB ✓ |
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| Syscall budget | <1e-7/op | Current 1.25e-7/op ✓ |
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---
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## Timeline
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- **Phase 62A (C7 ULTRA Inline)**: Single phase, 4-6 hours
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- **Decision point**: After A/B test
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- **Next phases**: Based on Phase 62A result
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