docs: clarify Phase 75 vs FAST PGO SSOT

CURRENT_TASK.md

@@ -2,13 +2,18 @@
 
 ## 0) 今の「正」（SSOT）
 
-- **性能比較の正**: FAST PGO build（`make pgo-fast-full` → `bench_random_mixed_hakmem_minimal_pgo`）＋ **WarmPool=16** + **C5+C6 inline slots**（Phase 75 強GOで昇格済み）
+- **性能比較の正**: FAST PGO build（`make pgo-fast-full` → `bench_random_mixed_hakmem_minimal_pgo`）＋ **WarmPool=16**
+  - Phase 75（C5/C6 inline slots）は presets に昇格済みだが、**FAST PGO での再計測（rebase）は未実施**（Standard での A/B は +5.41%）。
 - **安全・互換の正**: Standard build（`make bench_random_mixed_hakmem`）
 - **観測の正**: OBSERVE build（`make perf_observe`）
 - **スコアカード（目標/現在値）**: `docs/analysis/PERFORMANCE_TARGETS_SCORECARD.md`
-  - Current baseline（FAST v3 + PGO + Phase 75）: **44.65M ops/s = 36.75% of mimalloc** (Phase 75-3 4-point matrix)
-  - 次の目標: **M2 = 55%**（残り **+18.25pp**）
-- **Mixed 10-run SSOT**: `scripts/run_mixed_10_cleanenv.sh`（`ITERS=20000000 WS=400`、`HAKMEM_WARM_POOL_SIZE=16` + `C5_INLINE_SLOTS=1` + `C6_INLINE_SLOTS=1` デフォルト）
+  - **FAST baseline（SSOT）**: `docs/analysis/PERFORMANCE_TARGETS_SCORECARD.md` を正とする（Phase 69: 62.63M ops/s = 51.77% of mimalloc）
+  - **Phase 75 の計測**: `bench_random_mixed_hakmem`（非PGO/別ターゲット）で **A/B +5.41%** を確認（Phase 75-3 4-point matrix）。FAST PGO への反映（rebase）は別途。
+  - 次の目標: **M2 = 55%**（gap は FAST baseline を基準に判断する）
+- **Mixed 10-run SSOT（ハーネス）**: `scripts/run_mixed_10_cleanenv.sh`
+  - デフォルト `BENCH_BIN=./bench_random_mixed_hakmem`（Standard）
+  - FAST PGO は `BENCH_BIN=./bench_random_mixed_hakmem_minimal_pgo` を明示する
+  - 既定: `ITERS=20000000 WS=400`、`HAKMEM_WARM_POOL_SIZE=16`、`HAKMEM_TINY_C5_INLINE_SLOTS=1`、`HAKMEM_TINY_C6_INLINE_SLOTS=1`
 
 ## 1) 迷子防止（経路/観測）
 
@@ -84,7 +89,7 @@
 
 ---
 
-## Phase 75（構造）: Hot-class Inline Slots (P2) 🟡 **準備中**
+## Phase 75（構造）: Hot-class Inline Slots (P2) ✅ **完了（Standard A/B）**
 
 **Goal**: C4-C7 の統計分析 → targeted optimization 戦略決定
 
@@ -198,7 +203,8 @@ Per-class Unified-STATS (Mixed SSOT, WS=400, HAKMEM_MEASURE_UNIFIED_CACHE=1):
 2. `scripts/run_mixed_10_cleanenv.sh`: Added C5+C6 ENV defaults
 3. C5+C6 inline slots now **promoted to preset defaults** for MIXED_TINYV3_C7_SAFE
 
-**Phase 75 Complete**: C5+C6 inline slots (129-256B) deliver +5.41% proven gain. Baseline updated to 44.65 M ops/s.
+**Phase 75 Complete**: C5+C6 inline slots (129-256B) deliver +5.41% proven gain **on Standard binary**（`bench_random_mixed_hakmem`）。
+- FAST PGO baseline（スコアカード）を更新する前に、`BENCH_BIN=./bench_random_mixed_hakmem_minimal_pgo` で **同条件の A/B（C5/C6 OFF/ON）** を再計測すること。
 
 **参考**:
 - 4-point matrix 結果: `docs/analysis/PHASE75_3_C5_C6_INTERACTION_RESULTS.md`

docs/analysis/PERFORMANCE_TARGETS_SCORECARD.md

@@ -20,6 +20,10 @@ mimalloc との比較は **FAST build** で行う（Standard は fixed tax を
 - **Baseline binary**: `bench_random_mixed_hakmem_minimal_pgo` (Phase 68 upgraded)
 - **Stability**: Phase 66: 3 iterations, +3.0% mean, variance <±1% | Phase 68: 10-run, +1.19% vs Phase 66 (GO)
 
+Note:
+- Phase 75 introduced C5/C6 inline slots and promoted them into presets. Phase 75 A/B results were recorded on the Standard binary (`./bench_random_mixed_hakmem`).
+- FAST PGO SSOT baselines/ratios should only be updated after re-running A/B with `BENCH_BIN=./bench_random_mixed_hakmem_minimal_pgo`.
+
 ### hakmem Build Variants（同一バイナリレイアウト）
 
 | Build | Mean (M ops/s) | Median (M ops/s) | vs mimalloc | 備考 |

docs/analysis/PHASE75_2_C5_INLINE_SLOTS_IMPLEMENTATION.md

@@ -230,18 +230,15 @@ Expected behavior (Phase 73 winning thesis):
 ### Expected Performance Path
 
 ```
-Phase 75-0 baseline (Phase 69):  62.63 M ops/s
-Phase 75-1 (C6-only):            +2.87% → 64.43 M ops/s
-Phase 75-2 (C5-only):            +1.99% → 65.71 M ops/s (estimated from 44.62 → 45.51)
-Phase 75-3 (C5+C6 interaction):  Check for sub-additivity
+Phase 75-0 baseline (Point A):   42.36 M ops/s (Standard: ./bench_random_mixed_hakmem)
+Phase 75-1 (C6-only):            +2.87% (Standard A/B)
+Phase 75-2 (C5-only, isolated):  +1.10% (Standard A/B, with C6 already ON)
+Phase 75-3 (C5+C6 interaction):  validate sub-additivity via 4-point matrix
 ```
 
-**Note**: The baseline of 44.62 M ops/s is lower than expected. This may be due to:
-- Different benchmark parameters
-- ENV variables not matching Phase 69 baseline
-- Build configuration differences
-
-This should be investigated during the full test.
+**Note (SSOT)**:
+- Do not extrapolate Phase 75 from the FAST PGO baseline (Phase 69/68 scorecard numbers). Phase 75 must be measured on the **same binary** you care about.
+- To measure Phase 75 on FAST PGO, run the same A/B with `BENCH_BIN=./bench_random_mixed_hakmem_minimal_pgo`.
 
 ---
 
@@ -276,7 +273,7 @@ This should be investigated during the full test.
 ### Full Test Required ⏳
 
 - [ ] Run full 10-iteration test with proper ENV setup
-- [ ] Verify baseline matches expected Phase 69 performance
+- [ ] Verify baseline matches the selected SSOT harness + binary (`scripts/run_mixed_10_cleanenv.sh` + `BENCH_BIN=...`)
 - [ ] Confirm perf stat extraction is correct
 - [ ] Validate decision criteria
 
@@ -291,7 +288,7 @@ This should be investigated during the full test.
 - C6 inline slots: 128 slots × 8 bytes = 1KB
 - **Total C5+C6**: 2KB per thread
 
-**Justification**: 2KB is acceptable given the performance gains (+2.87% from C6, +1.99% from C5).
+**Justification**: 2KB is acceptable given the measured gains (+2.87% from C6 in Phase 75-1, +1.10% from C5 isolated in Phase 75-2).
 
 ### Integration Order
 

docs/analysis/PHASE75_3_C5_C6_INTERACTION_RESULTS.md

@@ -5,6 +5,10 @@
 **Decision**: **GO (promotion)**
 **Status**: C5+C6 inline slots promoted to core/bench_profile.h defaults
 
+**Measurement note (SSOT)**:
+- This document records results measured with the **Standard** benchmark binary (`./bench_random_mixed_hakmem`) unless explicitly overridden.
+- FAST PGO baseline tracking and mimalloc ratio remain in `docs/analysis/PERFORMANCE_TARGETS_SCORECARD.md` and require `BENCH_BIN=./bench_random_mixed_hakmem_minimal_pgo`.
+
 ---
 
 ## Executive Summary
@@ -214,21 +218,15 @@ Throughput: 42.18 M ops/s
 
 | Phase | Test | Result | Decision |
 |-------|------|--------|----------|
-| **75-1** | C6 baseline A/B (10-run) | +2.87% | GO (promoted) |
-| **75-2** | C5 baseline A/B (10-run) | +2.78% | GO (promoted) |
+| **75-1** | C6-only A/B (10-run) | +2.87% | GO (promoted) |
+| **75-2** | C5-only isolated A/B (10-run, with C6 already ON) | +1.10% | GO (promoted) |
 | **75-3** | C5+C6 interaction (4-point matrix) | +5.41% | **GO (promoted)** |
 
 **Phase 75 Final Outcome**:
 - **Baseline (Phase 75-0)**: 42.36 M ops/s (implicit from Point A)
 - **Phase 75 Final (C5+C6)**: 44.65 M ops/s
 - **Total Gain**: +5.41% (+2.29 M ops/s)
-- **mimalloc target (121.5 M ops/s)**: 44.65 / 121.5 = **36.75% of mimalloc** (up from ~35% baseline)
-
-**M2 Progress Check**:
-- M2 target: 55% of mimalloc ≈ 66.8 M ops/s
-- Current: 44.65 M ops/s (36.75% of mimalloc)
-- Remaining gap: 66.8 - 44.65 = 22.15 M ops/s (~49.6% gain needed)
-- Gap to M2: 55% - 36.75% = **18.25pp** (percentage points)
+- **mimalloc ratio / M2 progress**: N/A in this document (measured on Standard binary). Track via FAST PGO SSOT in `docs/analysis/PERFORMANCE_TARGETS_SCORECARD.md`.
 
 **Phase 75 demonstrates**: Inline slot optimization is a viable path. C5+C6 provide a +5.41% platform for next optimizations.
 

docs/analysis/PHASE75_COMPLETE_SUMMARY.md

@@ -0,0 +1,402 @@
+# Phase 75: Hot-class Inline Slots - Complete Summary
+
+**Status**: ✅ **PHASE 75 COMPLETE** - Strong GO (+5.41%), promoted to defaults
+
+**Timeline**: Phase 75-0 → Phase 75-3 (Sequential)
+**Test Methodology**: Data-driven per-class targeting + 4-point matrix interaction test
+**Final Decision**: STRONG GO - C5+C6 inline slots promoted to core/bench_profile.h preset defaults
+
+---
+
+## Executive Summary
+
+**Phase 75 successfully opened a new optimization axis** by targeting individual allocation classes (C5, C6) with thread-local inline slot rings. Through systematic per-class analysis, isolated A/B testing, and comprehensive interaction testing, Phase 75 achieved:
+
+- **+5.41% throughput improvement** (D vs A: 42.36 → 44.65 M ops/s)
+- **Near-perfect additivity** (1.72% sub-additivity between C5 and C6)
+- **Validated Phase 73 hypothesis**: Function call elimination reduces instructions/branches while maintaining cache efficiency
+- **Promotion to defaults**: C5+C6 inline slots now built-in to `MIXED_TINYV3_C7_SAFE` preset
+
+**Important measurement note (SSOT)**:
+- The Phase 75 A/B numbers in this document were measured with the **Standard** benchmark binary: `./bench_random_mixed_hakmem`.
+- They are **not directly comparable** to the FAST PGO baseline (`./bench_random_mixed_hakmem_minimal_pgo`) tracked in `docs/analysis/PERFORMANCE_TARGETS_SCORECARD.md`.
+- To rebase Phase 75 onto FAST PGO, re-run the same A/B using:
+  - `BENCH_BIN=./bench_random_mixed_hakmem_minimal_pgo scripts/run_mixed_10_cleanenv.sh`
+  - and toggle `HAKMEM_TINY_C5_INLINE_SLOTS` / `HAKMEM_TINY_C6_INLINE_SLOTS`.
+
+---
+
+## Phase 75 Journey
+
+### Phase 75-0: Per-Class Analysis (Foundation)
+
+**Goal**: Determine which C4-C7 classes are most active in Mixed SSOT workload
+
+**Methodology**: OBSERVE run with `HAKMEM_MEASURE_UNIFIED_CACHE=1` to gather per-class Unified-STATS
+
+**Results** (per-class operation volume):
+
+| Class | Hits | Pushes | Total Ops | % of C4-C7 | Hit Rate | Capacity |
+|-------|------|--------|-----------|-----------|----------|----------|
+| **C6** | 2,750,854 | 2,750,855 | 5,501,709 | **57.2%** | 100% | 128 |
+| **C5** | 1,373,604 | 1,373,605 | 2,747,209 | **28.5%** | 100% | 128 |
+| **C4** | 687,563 | 687,564 | 1,375,127 | **14.3%** | 100% | 64 |
+| **C7** | ? | ? | ? | ? | ? | ? |
+
+**Key Finding**: C6 dominates with **57.2% of C4-C7 operations**. Both C5 and C6 show 100% hit rates with near-capacity occupancy (98-99%).
+
+**Decision**: Target C6 first (highest volume), then C5 (second-highest), isolating individual contributions before combining.
+
+### Phase 75-1: C6-only Inline Slots
+
+**Goal**: Validate inline slot optimization on highest-volume class (C6, 57.2% of ops)
+
+**Approach**: Modular box theory with 5 new components:
+1. ENV gate box: `HAKMEM_TINY_C6_INLINE_SLOTS` (lazy-init)
+2. TLS extension box: 128-slot FIFO ring (1KB per thread)
+3. Fast-path API: `c6_inline_push/pop` (always_inline, 1-2 cycles)
+4. Integration box: Single boundary per operation (alloc/free)
+5. Test script: Automated A/B with decision gate
+
+**Test Methodology**: Baseline (C6=OFF) vs Treatment (C6=ON), 10-run Mixed SSOT
+
+**Results**:
+
+| Metric | Baseline | Treatment | Delta |
+|--------|----------|-----------|-------|
+| Throughput | 44.24 M ops/s | 45.51 M ops/s | **+2.87%** |
+| Instructions | Unchanged (implies) | Implies optimized | - |
+| Branches | Unchanged (implies) | Implies optimized | - |
+
+**Decision**: ✅ **GO** - Exceeds +1.0% strict threshold for structural change
+
+**Mechanism**: Eliminated `unified_cache_enabled()` check in hot loop for C6 allocations via ring buffer direct access
+
+---
+
+### Phase 75-2: C5-only Inline Slots (Isolated)
+
+**Goal**: Measure C5 individual contribution (28.5% of C4-C7 ops) without confounding with C6
+
+**Approach**: Replicate C6 pattern for C5 class (128 slots, 1KB TLS)
+
+**Test Methodology**: Carefully isolated A/B
+- **Baseline**: C5=OFF, C6=ON (from Phase 75-1)
+- **Treatment**: C5=ON, C6=ON (additive measurement)
+
+**This isolates C5's independent contribution separate from C6's already-proven +2.87%**
+
+**Results** (10-run Mixed SSOT):
+
+| Metric | Baseline (C5=OFF, C6=ON) | Treatment (C5=ON, C6=ON) | Delta |
+|--------|--------------------------|--------------------------|-------|
+| Throughput | 44.26 M ops/s (σ=0.37) | 44.74 M ops/s (σ=0.54) | **+1.10%** |
+
+**Decision**: ✅ **GO** - Exceeds +1.0% GO threshold
+
+**Key Insight**: C5 contributes +1.10% independently, validating per-class targeting as viable optimization axis
+
+---
+
+### Phase 75-3: C5+C6 Interaction Test (4-Point Matrix)
+
+**Goal**: Measure true cumulative effect, validate additivity, and make final promotion decision
+
+**Methodology**: 4-point matrix using **single binary** with ENV-only configuration
+
+| Point | C5 | C6 | Config | Purpose |
+|-------|----|----|--------|---------|
+| **A** | 0 | 0 | Baseline | Ground truth |
+| **B** | 1 | 0 | C5 solo | C5 contribution in full matrix |
+| **C** | 0 | 1 | C6 solo | C6 contribution in full matrix |
+| **D** | 1 | 1 | C5+C6 | Combined (interaction measurement) |
+
+**Test Conditions**:
+- Single compiled binary (C5+C6 code both present)
+- All 4 points via ENV variables only (no rebuild)
+- 10 runs per point = 40 total runs
+- All sequential in single session (minimize noise)
+
+**Results** (10-run per point, Mixed SSOT, WS=400):
+
+| Point | Config | Avg (M ops/s) | vs A | Interpretation |
+|-------|--------|---------------|------|----------------|
+| **A** | C5=0, C6=0 | **42.36** | -- | Complete baseline |
+| **B** | C5=1, C6=0 | **43.54** | **+2.79%** | C5 solo in full system |
+| **C** | C5=0, C6=1 | **44.25** | **+4.46%** | C6 solo in full system |
+| **D** | C5=1, C6=1 | **44.65** | **+5.41%** | **COMBINED TARGET** |
+
+**Additivity Analysis**:
+
+```
+Expected additive (no interaction):
+  D_expected = B + C - A
+            = 43.54 + 44.25 - 42.36
+            = 45.43 M ops/s
+
+Actual measured:
+  D_actual = 44.65 M ops/s
+
+Sub-additivity (diminishing returns):
+  Sub = (45.43 - 44.65) / 45.43 × 100%
+      = 1.72%
+
+Interpretation:
+  - Near-perfect additivity
+  - Minimal negative interaction (< 2% diminishing returns)
+  - C5 and C6 optimizations are highly orthogonal
+```
+
+**Perf Stat Validation** (Point D only, representative run):
+
+| Metric | Point D (C5+C6) | Point A (Baseline) | Delta | Phase 73 Thesis |
+|--------|-----------------|-------------------|-------|-----------------|
+| Instructions | 4.415B | 4.703B | **-6.1%** | ✓ DOWN as predicted |
+| Branches | 1.216B | 1.295B | **-6.1%** | ✓ DOWN as predicted |
+| Cache-misses | 510K | 745K | **-31.5%** | ✓ No explosion (vs Phase 74-2: +86%) |
+| Throughput | 44.00 M/s | 42.18 M/s | **+4.3%** | ✓ Net positive |
+
+**Phase 73 Hypothesis Validation**: ✅ CONFIRMED
+- Function call elimination reduces instructions/branches (-6.1%)
+- No cache-miss explosion (improved locality instead)
+- Net positive throughput (+5.41%)
+
+**Decision**: ✅ **STRONG GO (+5.41%)**
+
+| Criterion | Threshold | Result | Pass |
+|-----------|-----------|--------|------|
+| D vs A throughput | ≥ +3.0% | **+5.41%** | ✅ |
+| Sub-additivity | ≤ 20% | **1.72%** | ✅ |
+| Instructions | Decrease or flat | **-6.1%** | ✅ |
+| Branches | Decrease or flat | **-6.1%** | ✅ |
+| Cache-misses | No spike | **-31.5%** | ✅ |
+
+All criteria passed → **PROMOTION APPROVED**
+
+---
+
+## Promotion Implementation
+
+### File Changes
+
+**1. `core/bench_profile.h`** - Added C5+C6 defaults to preset
+
+```c
+// Phase 75-3: C5+C6 Inline Slots (STRONG GO +5.41%, 4-point matrix A/B)
+bench_setenv_default("HAKMEM_TINY_C5_INLINE_SLOTS", "1");
+bench_setenv_default("HAKMEM_TINY_C6_INLINE_SLOTS", "1");
+```
+
+**2. `scripts/run_mixed_10_cleanenv.sh`** - Added ENV defaults for SSOT reproducibility
+
+```bash
+# Phase 75-3: C5+C6 Inline Slots (STRONG GO +5.41%)
+export HAKMEM_TINY_C5_INLINE_SLOTS=${HAKMEM_TINY_C5_INLINE_SLOTS:-1}
+export HAKMEM_TINY_C6_INLINE_SLOTS=${HAKMEM_TINY_C6_INLINE_SLOTS:-1}
+```
+
+**3. `CURRENT_TASK.md`** - Updated baseline and SSOT
+
+```
+- Phase 75 results were confirmed on Standard binary (non-PGO).
+- Mixed 10-run harness: WarmPool=16 + C5_INLINE_SLOTS=1 + C6_INLINE_SLOTS=1
+```
+
+### Implementation Principle
+
+**Minimal change, maximum clarity**:
+- Only ENV defaults added (no code path changes to defaults)
+- Backward compatible (ENV=0 still available for opt-out)
+- SSOT reproducibility maintained in run_mixed_10_cleanenv.sh
+- No deletion of legacy code
+
+---
+
+## Phase 75 Cumulative Performance
+
+### Journey Through Phases
+
+| Phase | What | Result | Type | Status |
+|-------|------|--------|------|--------|
+| 75-0 | Per-class analysis | C6: 57.2%, C5: 28.5% | Analysis | Input |
+| 75-1 | C6-only A/B test | +2.87% | Standalone | GO |
+| 75-2 | C5-only A/B test (isolated) | +1.10% | Standalone | GO |
+| 75-3 | C5+C6 interaction (4-point) | +5.41% | Combined | STRONG GO |
+
+### Performance Trajectory
+
+```
+Phase 75-0 baseline:    42.36 M ops/s (reference, Point A)
+Phase 75-1 (C6):        44.25 M ops/s (+4.46% from Point A)
+Phase 75-2 (C5 iso):    44.74 M ops/s (+5.64% from Phase 75-0)
+Phase 75-3 (C5+C6):     44.65 M ops/s (+5.41% from Phase 75-0) [FINAL]
+```
+
+### Baseline Evolution
+
+```
+Pre-Phase 75 (implicit):  ~42.0 M ops/s
+Phase 75-3 final:         44.65 M ops/s
+Improvement:              +2.65 M ops/s (+6.3% from pre-phase baseline)
+```
+
+---
+
+## Comparison: mimalloc Positioning
+
+### mimalloc Baseline Reference
+
+Test machine (from prior benchmarks): **mimalloc ≈ 121.5 M ops/s** (Mixed SSOT)
+
+### hakmem Evolution
+
+| Phase | Throughput | % of mimalloc | Gap to M2 |
+|-------|-----------|---------------|-----------|
+| Phase 69 (WarmPool=16) | 62.63 M ops/s | 51.54% | +3.46pp |
+| Phase 72 (WarmPool sweep) | ~62.63 M ops/s | 51.54% | +3.46pp |
+| Phase 74 (hit-path opt) | ~62.63 M ops/s | 51.54% | +3.46pp |
+| **Phase 75 final (Standard)** | **44.65 M ops/s** | **N/A** | **N/A** |
+
+**Note**:
+- Phase 75-3 was measured on **Standard** binary, so the mimalloc ratio is **N/A** here.
+- Actual M2 progress should be tracked using the FAST PGO SSOT baseline in `docs/analysis/PERFORMANCE_TARGETS_SCORECARD.md`.
+
+---
+
+## Key Lessons Learned
+
+### 1. Per-Class Targeting Opens New Optimization Axis
+
+**Phase 74 vs Phase 75**:
+- Phase 74: Generic UnifiedCache hit-path optimization → NEUTRAL/NO-GO (register pressure, cache-miss sensitivity)
+- Phase 75: Per-class targeting with class-specific resources (TLS rings) → +5.41% STRONG GO
+
+**Insight**: Not all optimizations apply equally to all classes. Class-specific optimization can succeed where generic approaches fail.
+
+### 2. Isolated A/B Testing is Essential
+
+**Phase 75-2 design (C5-only with C6=ON baseline)**:
+- Avoids confounding individual contributions
+- Validates orthogonality of optimizations
+- Enables data-driven decision making
+
+**Without isolation**: Would not know if C5 added +1.10% independent value or was purely additive artifact.
+
+### 3. 4-Point Matrix Reveals Interaction Effects
+
+**Phase 75-3 methodology**:
+- Single binary, ENV-only configuration
+- Points A, B, C, D form complete interaction matrix
+- Sub-additivity analysis (1.72%) confirms orthogonality
+- Fail-fast fallback (ring FULL → unified_cache) keeps system stable
+
+**Insight**: Compound optimizations need rigorous interaction testing. 1.72% sub-additivity is excellent; 20%+ would be concerning.
+
+### 4. Function Call Elimination Thesis (Phase 73) Validated
+
+**Hardware counter confirmation (Point D vs A)**:
+- Instructions: -6.1% (function calls eliminated)
+- Branches: -6.1% (fewer checks/jumps)
+- Cache-misses: -31.5% (not +86% like Phase 74-2)
+- Throughput: +5.41% (net positive)
+
+**Mechanism**: Inline slot rings replace function calls to unified_cache, reducing control flow overhead while improving cache behavior.
+
+### 5. Modular Box Theory Enables Fast Iteration
+
+**Phase 75 implementation (3 phases in ~1 session)**:
+- Clean separation: ENV box, TLS box, API box, integration box
+- Low coupling: each phase replicates pattern, no complex interactions
+- Easy rollback: ENV gates allow instant disable without rebuild
+- Fail-fast: graceful degradation on resource exhaustion (ring FULL)
+
+---
+
+## Next Steps (Phase 76+)
+
+### Options for Continued M2 Progress
+
+With C5+C6 now providing **+5.41% platform**, remaining gap to M2 (55% of mimalloc) is **18.25pp**.
+
+### Path A: C4 Inline Slots (High Risk, High Reward)
+
+**Background**: Phase 74-2 showed +4.31% but with **+86% cache-misses** (register pressure from local variables).
+
+**Redesign opportunity**:
+- Smaller slots? (C4 is 257-512B, larger than C5/C6)
+- Partial inline? (not all 64 slots, just hot subset)
+- Different strategy? (not ring buffer, something more cache-friendly)
+- Separate TLS layout? (to reduce contention with C5/C6 rings)
+
+**Risk**: High (Phase 74 experience)
+**Potential**: +2-3% if redesign succeeds
+
+### Path B: C7 Inline Slots (Unknown)
+
+**Background**: C7 statistics not yet gathered; high-frequency allocations (1-8B)
+
+**Investigation needed**:
+- Per-class analysis similar to Phase 75-0
+- Determine if C7 is allocator-intensive or rare
+- Design consideration: cache line alignment, contention with C5/C6
+
+**Risk**: Medium (pattern proven, but C7 is different size class)
+**Potential**: Unknown until analysis
+
+### Path C: Alternative Optimization Axes
+
+**Beyond inline slots**:
+- Metadata cache improvements
+- TLS layout optimization (reduce cache line bouncing)
+- Free path specialization
+- Carving/batching optimizations
+- Backend allocation strategy
+
+**Risk**: Medium (unproven in Phase 75-3 session)
+**Potential**: Highly variable
+
+---
+
+## Artifacts
+
+### Test Scripts
+- `scripts/phase75_3_matrix_test.sh` - 4-point matrix A/B automation
+- `scripts/phase75_c6_inline_test.sh` - Phase 75-1 C6 isolation test
+- `scripts/phase75_c5_inline_test.sh` - Phase 75-2 C5 isolation test
+
+### Documentation
+- `docs/analysis/PHASE75_PERCLASS_ANALYSIS_0_SSOT.md` - Phase 75-0 per-class findings
+- `docs/analysis/PHASE75_C6_INLINE_SLOTS_1_RESULTS.md` - Phase 75-1 results
+- `docs/analysis/PHASE75_2_C5_INLINE_SLOTS_IMPLEMENTATION.md` - Phase 75-2 implementation
+- `docs/analysis/PHASE75_3_C5_C6_INTERACTION_RESULTS.md` - Phase 75-3 4-point matrix results
+
+### Code Changes
+- `core/box/tiny_c6_inline_slots_env_box.h` - C6 ENV gate
+- `core/box/tiny_c6_inline_slots_tls_box.h` - C6 TLS ring
+- `core/front/tiny_c6_inline_slots.h` - C6 fast-path API
+- `core/box/tiny_c5_inline_slots_env_box.h` - C5 ENV gate
+- `core/box/tiny_c5_inline_slots_tls_box.h` - C5 TLS ring
+- `core/front/tiny_c5_inline_slots.h` - C5 fast-path API
+- `core/tiny_c5_inline_slots.c` - C5 TLS variable
+- `core/tiny_c6_inline_slots.c` - C6 TLS variable (implicit via Phase 75-1)
+- `core/box/tiny_front_hot_box.h` - Alloc integration (both C5, C6)
+- `core/box/tiny_legacy_fallback_box.h` - Free integration (both C5, C6)
+- `Makefile` - Build configuration
+
+### Git Commits
+- `0009ce13b` - Phase 75-1: C6-only (+2.87% GO)
+- `043d34ad5` - Phase 75-2: C5-only (+1.10% GO)
+- `4f99054fd` - Phase 75-3: 4-point matrix (+5.41% STRONG GO, promoted)
+
+---
+
+## Conclusion
+
+**Phase 75 successfully validated hot-class inline slots as a new optimization axis**, achieving **+5.41% throughput improvement** with **near-perfect additivity** and **validation of Phase 73 function call elimination thesis**.
+
+C5+C6 inline slots are now **promoted to core/bench_profile.h preset defaults**, providing a stable **+5.41% platform** for future optimizations toward M2 (55% of mimalloc).
+
+**Status**: ✅ **PHASE 75 COMPLETE**
+**Standard A/B baseline (Point D)**: 44.65 M ops/s (`./bench_random_mixed_hakmem`)
+**FAST PGO baseline / M2 gap**: Track via `docs/analysis/PERFORMANCE_TARGETS_SCORECARD.md` (requires `BENCH_BIN=./bench_random_mixed_hakmem_minimal_pgo`)
+**Next**: Phase 75-4 (FAST PGO rebase) → then Phase 76 (C4 redesign, C7 analysis, or alternative axes)

docs/analysis/PHASE75_PERCLASS_ANALYSIS_0_SSOT.md

@@ -122,15 +122,21 @@ Assuming **inline fast-path** placement (TLS-direct, zero-branch):
 
 ## 6. Before/After Unified-STATS Baseline
 
-### Current Baseline (Phase 69: WarmPool=16)
+### FAST PGO Baseline Reference (Phase 69: WarmPool=16)
+
+**Important (SSOT)**:
+- This baseline is from the FAST PGO scorecard and is the correct reference for mimalloc ratio tracking.
+- If you run `scripts/run_mixed_10_cleanenv.sh` without setting `BENCH_BIN`, it defaults to the Standard binary (`./bench_random_mixed_hakmem`).
+- To measure Phase 75 on FAST PGO, set:
+  - `BENCH_BIN=./bench_random_mixed_hakmem_minimal_pgo scripts/run_mixed_10_cleanenv.sh`
 
 ```
-Mixed SSOT Throughput: 62.63 M ops/s (51.77% of mimalloc)
+FAST Mixed SSOT Throughput: 62.63 M ops/s (51.77% of mimalloc)
 Target M2: 55% of mimalloc (~65.1 M ops/s baseline)
 Remaining gap: +3.23pp
 ```
 
-### Phase 75 (P2) Success Criteria
+### Phase 75 (P2) Success Criteria (measured vs FAST PGO baseline)
 
 | Scenario | Throughput | vs Baseline | Status |
 |----------|-----------|-----------|--------|