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Phase 70-73: Route banner + observe stats consistency + WarmPool analysis SSOT

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Observability infrastructure:
- Route Banner (ENV: HAKMEM_ROUTE_BANNER=1) for runtime configuration display
- Unified Cache consistency check (total_allocs vs total_frees)
- Verified counters are balanced (5.3M allocs = 5.3M frees)

WarmPool=16 comprehensive analysis:
- Phase 71: A/B test confirmed +1.31% throughput, 2.4x stability improvement
- Phase 73: Hardware profiling identified instruction reduction as root cause
  * -17.4M instructions (-0.38%)
  * -3.7M branches (-0.30%)
  * Trade-off: dTLB/cache misses increased, but instruction savings dominate
- Phase 72-0: Function-level perf record pinpointed unified_cache_push
  * Branches: -0.86% overhead (largest single-function improvement)
  * Instructions: -0.22% overhead

Key finding: WarmPool=16 optimization is control-flow based, not memory-hierarchy based.
Full analysis: docs/analysis/PHASE70_71_WARMPOOL16_ANALYSIS.md
This commit is contained in:
Moe Charm (CI)
2025-12-18 05:55:27 +09:00
parent f506ecfc0a
commit 8fdbc6d07e
3 changed files with 1049 additions and 3 deletions
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25
core/front/tiny_unified_cache.c
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@ -265,6 +265,31 @@ void unified_cache_print_stats(void) {
#if !HAKMEM_BUILD_RELEASE || HAKMEM_UNIFIED_CACHE_STATS_COMPILED
fprintf(stderr, "\n[Unified-STATS] Unified Cache Metrics:\n");
// Phase 70-3: Consistency Check - calculate totals across all classes
uint64_t total_allocs_all = 0;
uint64_t total_frees_all = 0;
for (int cls = 0; cls < TINY_NUM_CLASSES; cls++) {
total_allocs_all += g_unified_cache_hit[cls] + g_unified_cache_miss[cls];
total_frees_all += g_unified_cache_push[cls] + g_unified_cache_full[cls];
}
// Print consistency check BEFORE individual class stats
fprintf(stderr, "[Unified-STATS] Consistency Check:\n");
fprintf(stderr, "[Unified-STATS] total_allocs (hit+miss) = %llu\n",
(unsigned long long)total_allocs_all);
fprintf(stderr, "[Unified-STATS] total_frees (push+full) = %llu\n",
(unsigned long long)total_frees_all);
// Phase 70-3: WARNING logic for inconsistent counters
static int g_consistency_warned = 0;
if (!g_consistency_warned && total_allocs_all > 0 && total_frees_all > total_allocs_all * 2) {
fprintf(stderr, "[Unified-STATS-WARNING] total_frees >> total_allocs detected! "
"Alloc counters may not be wired.\n");
g_consistency_warned = 1;
}
fprintf(stderr, "\n");
for (int cls = 0; cls < TINY_NUM_CLASSES; cls++) {
uint64_t total_allocs = g_unified_cache_hit[cls] + g_unified_cache_miss[cls];
uint64_t total_frees = g_unified_cache_push[cls] + g_unified_cache_full[cls];